System-on-chip test architectures nanometer design for testability /

Corporate Author: ebrary, Inc.
Other Authors: Stroud, Charles E.
Format: Book
Language:English
Published: Amsterdam ; Boston : Morgan Kaufmann Publishers, c2008.
Series:The Morgan Kaufmann series in systems on silicon
Subjects:
Online Access:http://site.ebrary.com/lib/ucy/Doc?id=10203465
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020 |z 9780123739735 (hardcover : alk. paper) 
040 |a CaPaEBR  |z 012373973X (hardcover : alk. paper) 
050 1 4 |a TK7895.E42  |b S978 2008eb 
245 0 0 |a System-on-chip test architectures  |b nanometer design for testability /  |c edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. 
260 |a Amsterdam ;  |b Morgan Kaufmann Publishers,  |c c2008.  |a Boston : 
300 |a xxxvi, 856 p. :  |b ill. 
490 1 |a The Morgan Kaufmann series in systems on silicon 
504 |a Includes bibliographical references and index. 
650 0 |a Systems on a chip  |x Testing. 
650 0 |a Integrated circuits  |x Very large scale integration  |x Testing. 
650 0 |a Integrated circuits  |x Very large scale integration 
700 1 |a Stroud, Charles E.  |x Design. 
710 2 |a ebrary, Inc. 
856 4 0 |u http://site.ebrary.com/lib/ucy/Doc?id=10203465 
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