Design verification with e/
Main Author: | Palnitkar, Samir |
---|---|
Format: | Book |
Language: | English |
Published: |
Upper Saddle River, NJ:
Prentice Hall PTR,
c2004
|
Subjects: |
Similar Items
-
Writing testbenches functional verification of HDL models /
by: Bergeron, Janick.
Published: (2002) -
Writing testbenches: functional verification of HDL models/
by: Bergeron, Janick
Published: (2003) -
Systemverilog for verification: a guide to learning the testbench language features/
by: Spear, Chris
Published: (2006) -
Verification plans: the five-day verification strategy for modern hardware verification languages/
by: James, Peet
Published: (2004) -
Principles of functional verification/
by: Meyer, Andreas S.
Published: (2004)