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System-on-a-chip : design and test /

Main Author: Rajsuman, Rochit.
Format: Book
Language:English
Published: Boston, MA : Artech House, 2000.
Series:Artech House signal processing library
Subjects:
Embedded computer systems > Design and construction.
Embedded computer systems > Testing.
Application-specific integrated circuits > Design and construction.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic.
COMPUTERS > Logic Design.
Systèmes enfouis (informatique) > Conception et construction.
Systèmes enfouis (informatique) > Essais.
Circuits intégrés à la demande > Conception et construction.
Online Access:http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=67446
Table of Contents:
  • Design
  • Architecture of the present-day SoC
  • Design issues of SoC
  • Hardware-software codesign
  • Codesign flow
  • Codesign tools
  • Core libraries, EDA tools, and web pointers
  • Core libraries
  • EDA tools and vendors
  • Web pointers
  • Design methodology for logic cores
  • SoC design flow
  • General guidelines for design reuse
  • Synchronous design
  • Memory of mixed-signal design
  • On-chip buses
  • Clock distribution
  • Clear/set/reset signals
  • Physical design
  • Deliverable models
  • Design process for soft and firm cores
  • Design flow
  • Development process for soft/firm cores
  • RTL guidelines
  • Soft/firm cores productization
  • Design process for hard cores
  • Unique design issues in hard cores
  • Development process for hard cores
  • Sign-off checklist and deliverables
  • Sign-off checklist
  • Soft core deliverables
  • Hard core deliberables
  • System integration
  • Designing with hard cores
  • Designing with soft cores
  • System verification
  • Design methodology for memory and analog cores
  • Why large embeded memories
  • Design methodology for embedded memories
  • Circuit techniques
  • Memory compiler
  • Simulation models
  • Specifications of analog circuits
  • Analog-to-digital converter
  • Phase-locked loops
  • High-speech circuits
  • Rambus ASIC cell
  • IEEE 1394 serial bus (Firewire) PHY layer
  • High-Speed I/O
  • Design validation
  • Core-level validation
  • Core validation plan
  • Testbenches
  • Core-level timing verification
  • Core interface verification
  • Protocol verification
  • Gate-level simulation
  • SoC design validation
  • Cosimulation
  • Emulation
  • Hardware prototypes
  • Core and SoC design examples
  • Microprocessor cores
  • V830R/AV superscaler RISC core
  • Design of powerPC 603e core
  • Comments of memory core generation
  • Core integration and on-chip bus
  • Examples of SoC
  • Media processors
  • Testbility of set-top box SoC
  • Testing of digital logic cores
  • SoC test issues
  • Access, control, and isolation
  • IEEE P1500 effort
  • Cores without boundary scan
  • Core test language
  • Core with boundary scan
  • Core test and IP protection
  • Test methodology for design reuse
  • Guidelines for core testability
  • High-level test synthesis
  • Testing of microprocessor cores
  • Built-in self-test method
  • Examples: testability features of ARM processor core
  • Debug support for microprocessor cores
  • Testing of embedded memories
  • Memory fault models and test algorithms
  • Fault models
  • Test algorithms
  • Effectiveness of test algorithms
  • Modification with multiple data background
  • Modification for multiport memories
  • Algorithm for double-buffered memories
  • Test methods for embedded memories
  • Testing through ASIC functional test
  • Test application by direct access
  • Test application by scan or collar register
  • Memory built-in self-test
  • Testing by on-chip microprocessor
  • Summary of test methods for embedded memories
  • Memory redundancy and repair
  • Hard repair
  • soft repair
  • mError detection and correction codes
  • Production testing of SoC with large embedded memory
  • Testing of analog and mixed-signal cores
  • Analog parameters and characterization
  • Digital-to-analog converter
  • Analog-to-digital converter
  • Phase-locked loop
  • Design-for-test and buil-in self-test methods for analog cores
  • Fluence technology's analog BIST
  • LogiVision's analog BIST
  • Testing by on-chip microprocessor
  • IEEE P1149.4
  • Testing of specific analog circuits
  • Rambus ASIC cell
  • Teting of 1394 serial bus/firewire
  • Iddq testing
  • Physical defects
  • Bridging (shorts)
  • Gate-oxide defects
  • Open (breaks)
  • Effectiveness of iddq testing
  • Iddq testing difficulties in SoC
  • Design-for-iddq-testing
  • Iddq test vector generation
  • Production testing
  • Production test flow
  • At-speed testing
  • RTD and dead cycles
  • Fly-by
  • Speed binning
  • Production throughput and materials handling
  • Test logistics
  • Tester setup
  • Multi-DUT testing.

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