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05695nam a2200361 a 4500 |
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1891460 |
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20171111234719.0 |
| 008 |
020517s2000 maua ob 001 0 eng d |
| 020 |
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|a 1580534716
|q (electronic bk.)
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| 020 |
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|a 9781580534710
|q (electronic bk.)
|z 1580531075
|q (alk. paper)
|q (alk. paper)
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| 040 |
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|a N$T
|b eng
|e pn
|z 9781580531078
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| 050 |
|
4 |
|a TK7895.E42
|b R37 2000eb
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| 100 |
1 |
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|a Rajsuman, Rochit.
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| 245 |
1 |
0 |
|a System-on-a-chip :
|b design and test /
|c Rochit Rajsuman.
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| 260 |
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|a Boston, MA :
|b Artech House,
|c 2000.
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| 300 |
|
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|a 1 online resource (xiii, 277 pages) :
|b illustrations.
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| 490 |
1 |
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|a Artech House signal processing library
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| 504 |
|
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|a Includes bibliographical references and index.
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| 505 |
0 |
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|a Design -- Architecture of the present-day SoC -- Design issues of SoC -- Hardware-software codesign -- Codesign flow -- Codesign tools -- Core libraries, EDA tools, and web pointers -- Core libraries -- EDA tools and vendors -- Web pointers -- Design methodology for logic cores -- SoC design flow -- General guidelines for design reuse -- Synchronous design -- Memory of mixed-signal design -- On-chip buses -- Clock distribution -- Clear/set/reset signals -- Physical design -- Deliverable models -- Design process for soft and firm cores -- Design flow -- Development process for soft/firm cores -- RTL guidelines -- Soft/firm cores productization -- Design process for hard cores -- Unique design issues in hard cores -- Development process for hard cores -- Sign-off checklist and deliverables -- Sign-off checklist -- Soft core deliverables -- Hard core deliberables -- System integration -- Designing with hard cores -- Designing with soft cores -- System verification -- Design methodology for memory and analog cores -- Why large embeded memories -- Design methodology for embedded memories -- Circuit techniques -- Memory compiler -- Simulation models -- Specifications of analog circuits -- Analog-to-digital converter -- Phase-locked loops -- High-speech circuits -- Rambus ASIC cell -- IEEE 1394 serial bus (Firewire) PHY layer -- High-Speed I/O -- Design validation -- Core-level validation -- Core validation plan -- Testbenches -- Core-level timing verification -- Core interface verification -- Protocol verification -- Gate-level simulation -- SoC design validation -- Cosimulation -- Emulation -- Hardware prototypes -- Core and SoC design examples -- Microprocessor cores -- V830R/AV superscaler RISC core -- Design of powerPC 603e core -- Comments of memory core generation -- Core integration and on-chip bus -- Examples of SoC -- Media processors -- Testbility of set-top box SoC -- Testing of digital logic cores -- SoC test issues -- Access, control, and isolation -- IEEE P1500 effort -- Cores without boundary scan -- Core test language -- Core with boundary scan -- Core test and IP protection -- Test methodology for design reuse -- Guidelines for core testability -- High-level test synthesis -- Testing of microprocessor cores -- Built-in self-test method -- Examples: testability features of ARM processor core -- Debug support for microprocessor cores -- Testing of embedded memories -- Memory fault models and test algorithms -- Fault models -- Test algorithms -- Effectiveness of test algorithms -- Modification with multiple data background -- Modification for multiport memories -- Algorithm for double-buffered memories -- Test methods for embedded memories -- Testing through ASIC functional test -- Test application by direct access -- Test application by scan or collar register -- Memory built-in self-test -- Testing by on-chip microprocessor -- Summary of test methods for embedded memories -- Memory redundancy and repair -- Hard repair -- soft repair -- mError detection and correction codes -- Production testing of SoC with large embedded memory -- Testing of analog and mixed-signal cores -- Analog parameters and characterization -- Digital-to-analog converter -- Analog-to-digital converter -- Phase-locked loop -- Design-for-test and buil-in self-test methods for analog cores -- Fluence technology's analog BIST -- LogiVision's analog BIST -- Testing by on-chip microprocessor -- IEEE P1149.4 -- Testing of specific analog circuits -- Rambus ASIC cell -- Teting of 1394 serial bus/firewire -- Iddq testing -- Physical defects -- Bridging (shorts) -- Gate-oxide defects -- Open (breaks) -- Effectiveness of iddq testing -- Iddq testing difficulties in SoC -- Design-for-iddq-testing -- Iddq test vector generation -- Production testing -- Production test flow -- At-speed testing -- RTD and dead cycles -- Fly-by -- Speed binning -- Production throughput and materials handling -- Test logistics -- Tester setup -- Multi-DUT testing.
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| 650 |
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0 |
|a Embedded computer systems
|x Design and construction.
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| 650 |
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0 |
|a Embedded computer systems
|x Testing.
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| 650 |
|
0 |
|a Application-specific integrated circuits
|x Design and construction.
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| 650 |
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7 |
|a TECHNOLOGY & ENGINEERING
|x Electronics
|x Circuits
|x VLSI & ULSI.
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| 650 |
|
7 |
|a TECHNOLOGY & ENGINEERING
|x Electronics
|x Circuits
|x Logic.
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| 650 |
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7 |
|a COMPUTERS
|x Logic Design.
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| 650 |
|
7 |
|a Application-specific integrated circuits
|x Design and construction.
|
| 650 |
|
7 |
|a Embedded computer systems
|x Design and construction.
|
| 650 |
|
7 |
|a Embedded computer systems
|x Testing.
|
| 650 |
|
7 |
|a Systèmes enfouis (informatique)
|x Conception et construction.
|
| 650 |
|
7 |
|a Systèmes enfouis (informatique)
|x Essais.
|
| 650 |
|
7 |
|a Circuits intégrés à la demande
|x Conception et construction.
|
| 856 |
4 |
0 |
|a System-on-Chip.
|u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=67446
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| 952 |
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|a CY-NiOUC
|b 5a0464306c5ad14ac1eeac78
|c 998a
|d 945l
|e -
|t 1
|x m
|z Books
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