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| LEADER |
03104nam a2200349 a 4500 |
| 001 |
1900677 |
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20171111234734.0 |
| 008 |
050902s2005 enka fob 001 0 eng d |
| 020 |
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|a 1423723503
|q (electronic bk.)
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| 020 |
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|a 9781423723509
|q (electronic bk.)
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| 020 |
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|a 9780750677608
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| 020 |
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|a 0750677600
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| 020 |
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|a 0080477097
|q (electronic bk. ;
|q Adobe Reader)
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| 020 |
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|a 9780080477091
|q (electronic bk. ;
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| 040 |
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|a N$T
|b eng
|e pn
|q Adobe Reader)
|
| 050 |
|
4 |
|a TK7868.L6
|b Y34 2004eb
|
| 100 |
1 |
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|a Yanda, Richard F.
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| 245 |
1 |
0 |
|a Demystifying chipmaking /
|c Richard F. Yanda, Michael Heynes, Anne Miller.
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| 260 |
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|a Oxford :
|b Elsevier/Newnes,
|c ©2005.
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| 300 |
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|a 1 online resource (xvii, 256 pages) :
|b illustrations
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| 504 |
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|a Includes bibliographical references (pages 251-252) and index.
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| 505 |
0 |
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|a CH 1: IC Fabrication Overview / CH 2: Support Technologies / CH 3: Forming Wells / CH 4: Isolate Active Areas (Shallow Trench Isolation) / CH 5: Building the Transistors / CH 6: First Level Metallization / CH 7: Multilevel Metal Interconnects and Dual Damascene / CH 8: Test and Assembly / APPENDIX A: Science Overview / APPENDIX B: Plasma Etch Supplement to Chapter 4.
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| 505 |
0 |
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|a IC fabrication overview -- Introduction -- Support technologies -- Integrated circuit fabrication -- Test and assembly -- Summary -- Support technologies -- Introduction -- Contamination control -- Crystal growth and wafer preparation -- Circuit design -- Photomask and reticle preparation -- Forming wells -- Introduction -- Initial oxidation -- Photolithography -- Ion implantation -- Isolate active areas (shallow trench isolation) -- Introduction to shallow trench isolation -- Pad oxide growth -- Silicon Nitride deposition -- Photolithography for photo/etch -- From trenches in silicon dioxide -- Chemical mechanical polishing (CMP) to remove excess dioxide -- Wet etch removal of Silicon Nitride and pad oxide -- Building the transistors -- Introduction -- Thin film formation -- Poly gate formation -- Source/drain formation -- Salicide formation -- First level metallization -- Introduction -- Nitride and oxide depositions -- CMP planarization -- Photo/etch for contact holes -- Tungsten plug process -- Low-k dielectric process -- Copper first level interconnection process -- Multilevel metal interconnects and dual damascene -- Introduction -- Deposit barrier layer and intermetal dielectric -- Dual damascene process -- Form bonding pads -- Final passivation process -- Test and assembly -- Introduction -- Wafer and chip testing -- Assembly and packaging.
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| 650 |
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0 |
|a Logic circuits
|x Design and construction.
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| 650 |
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0 |
|a Metal oxide semiconductors, Complementary.
|
| 650 |
|
7 |
|a COMPUTERS
|x Machine Theory.
|
| 650 |
|
7 |
|a COMPUTERS
|x Computer Engineering.
|
| 650 |
|
7 |
|a COMPUTERS
|x Hardware
|x General.
|
| 650 |
|
7 |
|a Logic circuits
|x Design and construction.
|
| 700 |
1 |
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|a Heynes, Michael.
|
| 856 |
4 |
0 |
|a Miller, Anne K.
|u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=130229
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| 952 |
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|a CY-NiOUC
|b 5a0465bd6c5ad14ac1eed9d7
|c 998a
|d 945l
|e -
|t 1
|x m
|z Books
|
