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040626s2002 nyua gs 001 0 eng d |
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|z 0306476878
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|a CaPaEBR
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1 |
4 |
|a TK7885.7
|b .B47 2002eb
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| 100 |
1 |
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|a Bergeron, Janick.
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| 245 |
1 |
0 |
|a Writing testbenches
|b functional verification of HDL models /
|c Janick Bergeron.
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| 260 |
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|a New York :
|b Kluwer Academic,
|c c2002.
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| 300 |
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|a xxii, 354 p. :
|b ill.
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| 500 |
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|a Includes index.
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| 650 |
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0 |
|a Computer hardware description languages.
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| 650 |
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0 |
|a Integrated circuits
|x Verification.
|
| 710 |
2 |
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|a ebrary, Inc.
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| 856 |
4 |
0 |
|u http://site.ebrary.com/lib/ucy/Doc?id=10053397
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| 952 |
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|a CY-NiOUC
|b 5a0457a76c5ad14ac1ecfcf6
|c 998a
|d 945l
|e -
|t 1
|x m
|z Books
|
