RISC architectures= Les architectures Risc/

Main Author: Heudin, J. C.
Other Authors: Panetto, C.
Format: Book
Language:English
Published: London: Chapman & Hall, c1992
Subjects:
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008 960322s1992 cy da er 000 u eng d
020 |a 0412453401  |q pbk 
040 |a CY  |b University of Cyprus  |e AACR-2 
050 |a TK895.M5H48 1992 
100 1 |a Heudin, J. C. 
240 1 4 |a Les architectures Risc 
245 1 0 |a RISC architectures=   |b Les architectures Risc/  |c J. C. Heudin and C. Panetto 
246 1 3 |a Les architectures Risc 
260 |a London:  |b Chapman & Hall,  |c c1992 
300 |a ix, 261 p. :  |b ill. ;  |c 24 cm. 
500 |a 'Translation of: Les architectures RISC.' 
500 |a Includes bibliographical references and index. 
650 0 |a Computer architecture 
650 0 |a Microprocessors 
650 0 |a Reduced instruction set computers 
700 1 |a Panetto, C. 
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