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00854nam a2200217 a 4500 |
| 001 |
1534790 |
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20171111233625.0 |
| 008 |
060302s2004 cy da r 000 u eng d |
| 020 |
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|a 0471441481
|q hbk.
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| 040 |
|
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|a CY
|b University of Cyprus
|e AACR2
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| 050 |
|
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|a TK7885.7.P37 2004
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| 050 |
|
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|a TK7885.7.P37 2004
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| 100 |
1 |
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|a Patmanapan, Ti Ar,
|d 1957-
|
| 245 |
1 |
0 |
|a Design through Verilog HDL/
|c T.R. Padmanabhan, B. Bala Tripura Sundari
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| 260 |
|
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|a Hoboken, NJ:
|b John Wiley ;
|c c2004
|a Piscataway, NJ:
|b IEEE Press,
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| 300 |
|
|
|a xii, 455 p. :
|b ill. ;
|c 24 cm.
|
| 500 |
|
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|a "Wiley-Interscience"--T.p.
|
| 504 |
|
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|a Includes bibliographical references (p. 449-450) and index.
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| 650 |
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0 |
|a Verilog (Computer hardware description language)
|
| 700 |
1 |
|
|a Tripura Sundari, B. Bala
|
| 952 |
|
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|a CY-NiOUC
|b 5a042ecc6c5ad14ac1e89072
|c 998a
|d 945l
|e TK7885.7.P37 2004
|t 1
|x m
|z Books
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