Χρίστου, Κ. Α. (2012). Path delay fault testing for digital VLSI circuits using specialized binary decision diagrams. Nicosia: [s. n.].
Chicago Style CitationΧρίστου, Κυριάκος Α. Path Delay Fault Testing for Digital VLSI Circuits Using Specialized Binary Decision Diagrams. Nicosia: [s. n.], 2012.
MLA CitationΧρίστου, Κυριάκος Α. Path Delay Fault Testing for Digital VLSI Circuits Using Specialized Binary Decision Diagrams. Nicosia: [s. n.], 2012.
Warning: These citations may not always be 100% accurate.